A Low Power Low Jitter CMOS Phase-Locked-Loop

The design and simulation of a low power low jitter PLL, which can operate in 1GHz to 2GHz frequency range, in a 0.35-μm CMOS technology is presented. To achieve high frequency of operation with low power dissipation, a two-stage ring oscillator is introduced. A new phase detector is also presented that can be used forhigh-speed data/clock recovery. In contrast to most existing structures, which their frequency of operation arelimited by sequential logic circuits, the new circuit exploits the leading and lagging signals from the VCO which greatly simplifies the phase detector structure. Furthermore the proposed structure by using an additional PDreduces the PLL’s pull-in time while maintains better noise bandwidth. The circuit dissipates a total power of 7.2mW from a 3.3-V supply

Keywords:

Voltage Controlled Oscillator , Phase Detector , Charge Pump filter , Jitter , Ring Oscillator