A Simulated Annealing-based Throughput-aware Task Mapping Algorithm for Manycore Processors

With the advent of having many processor cores on a single chip in many-core processors, the demand for exploiting these on-chip resources to boost the performance of applications has been increased. Task mapping is the problem of mapping the application tasks on these processor cores to achieve lower latency and better performance. Many researches are focused on minimizing the path between the tasks that demand high bandwidth for communication. Although using these methods can result in lower latency, but at the same time, it is possible to create congestion in the network which lowers the network throughput. In this paper, a throughput-aware method is proposed that uses simulated annealing for task mapping. The method is checked on several real-world applications and simulations are conducted on a cycle-accurate network on chip simulator. The results illustrate that the proposed method can achieve higher throughput while maintaining the delay in the NoC.

A Simulated Annealing-based Throughput-aware Task Mapping Algorithm for Manycore Processors Keywords:

Simulate annealing , Manycore processors , Task mapping