Two Dimensional Systolic Adaptive DLMS FIR Filters for Image Processing on FPGA

The aim of this paper is to hardware description and implementing of adaptive digital one- dimensional (1-D) and twodimensional (2-D) Finite Impulse Response (FIR) filters on FieldProgrammable Gate Array (FPGA) technology. The 2-D adaptive filter is particularly employed for image processing applicationsand a typical adaptive image noise cancellation application is considered. The delayed least mean square (DLMS) algorithm isused for updating filter weights in dynamic unknown environments. Some cell processors consisting a tree based systolic architecture are employed for improving speed of proposed 2-D filter for noisyimage processing. The VHDL hardware description language is employed for modeling and hardware description of differentschemes of filtering applications. The obtained results from the QUARTUS II tool on STRATIX II EP2S15F484C3 chip fromALTERA Inc. demonstrate a satisfactory performance of 2-D adaptive FIR filter for image noise cancellation in some wellknown image test-bench

Keywords:

Image Processing , Adaptive Filterin , FIR Filter , Two-dimensional Filter , Noise Cancellation , VHDL , FPGA