Magnitude Comparison and Sign Detection based on the ۴-Moduli Set {۲n+۱, ۲n−۱, ۲n+۳, ۲n−۳}

The ۴-moduli set residue number system (RNS),{۲n+۱, ۲n−۱, ۲n+۳, ۲n−۳}, with a wide dynamic range, has recently been proposed as a balanced ۴-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this ۴-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite ۱۴.۷ tool and the Spartan۶ family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a ۴۶% and ۲۸% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.

Keywords:

Residue Number System , Reverse Converter , Computer Arithmetic , Sign Detection