Design of an ultra low –power CMOS Comparator

In this paper, an ultra low –power CMOS Comparator circuit in the sub-threshold region is designed and simulated to minimize the power consumption . In this study, three comparator structures: HYBRID,SDPL and St-CMOS are introduced and the effect of power supply and temperature variations on the power consumption, delay, power-delay product and energy-delay product is analyzed and the simulation results are presented. Considering the simulation results, it is observed that SDPL technology obtains the least power consumption and and least delay and power delay product in comparison with other structures

Keywords:

CMOS , SDPL , HYBRID , Low-power , sub-threshold , comparator