Improvement of the Drive Current in ۵nm Bulk-FinFET Using Process and Device Simulations

Publish Year: 1399
نوع سند: مقاله ژورنالی
زبان: English
View: 55

This Paper With 18 Page And PDF Format Ready To Download

  • Certificate
  • من نویسنده این مقاله هستم

استخراج به نرم افزارهای پژوهشی:

لینک ثابت به این Paper:

شناسه ملی سند علمی:

JR_JOPN-5-1_005

تاریخ نمایه سازی: 25 بهمن 1402

Abstract:

Abstract: We present the optimization of the manufacturing process of the ۵nm bulk-FinFET technology by using the ۳D process and device simulations. In this paper, bysimulating the manufacturing processes, we focus on optimizing the manufacturingprocess to improve the drive current of the ۵nm FinFET. The improvement of drivecurrent is one of the most important issues in the FinFETs design. We first investigatethe impact of manufacturing process parameters include gate oxide thickness, type ofthe gate oxide, height of fin, and doping of the source and drain region on thresholdvoltage, breakdown voltage, and drive current of the transistor. Then, by selecting theoptimal parameters of the manufacturing process, we improve the drive current of the۵nm bulk-FinFET.

Authors

Payman Bahrami

Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran

Mohammad Reza Shayesteh

Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran

Majid Pourahmadi

Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran

Hadi Safdarkhani

Department of Electrical Engineering, Yazd University, Yazd, Iran

مراجع و منابع این Paper:

لیست زیر مراجع و منابع استفاده شده در این Paper را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود Paper لینک شده اند :
  • Self-heating effect modeling of a carbon nanotube-based fieldeffect transistor (CNTFET) [مقاله ژورنالی]
  • Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor [مقاله ژورنالی]
  • SP. Mohanty, Nanoelectronic mixed-signal system design, New York: McGraw-Hill Education, ...
  • W. Han, Toward Quantum FinFET, ZM. Wang, editor. Springer, ۲۰۱۳, ...
  • P. Mishra, A. Muttreja, N. K. Jha, FinFET circuit design, ...
  • R. Das, R. Goswami, and S. Baishya, Tri-gate heterojunction SOI ...
  • V. E. Dorgan, M.-H. Bae, and E. Pop, Mobility and ...
  • A. T. M. Fairus, V. K. Arora, Quantum engineering of ...
  • V. K. Arora, Theory of scattering-limited and ballistic mobility and ...
  • V. Kilchytska, S. Makovejev, S. Barraud, T. Poiroux, J.-P. Raskin, ...
  • J. Kedzierski, High-performance symmetric-gate and CMOS compatible Vt asymmetric-gate FinFET ...
  • X. Wang, A. R. Brown, B. Cheng, and A. Asenov, ...
  • I. Ferain, C. A. Colinge, and J.-P. Colinge, Multigate transistors ...
  • C. H. Wang, P.-F. Zhang, Three-dimensional DIBL for shallow-trench isolated ...
  • Threshold voltage roll-off compensation using back-gated MOSFET devices for system ...
  • S. Sengupta, S. Pandit, Study of LER/LWR induced V T ...
  • K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, ...
  • C. H. Jan, U. Bhattacharya, R. Brain, S.J. Choi, G. ...
  • M. Radosavljevic, G. Dewey, J. M. Fastenau, J. Kavalieros, R. ...
  • نمایش کامل مراجع