Low Power Design of Successive Approximation Registers
Publish place: 21th Iranian Conference on Electric Engineering
Publish Year: 1392
نوع سند: مقاله کنفرانسی
زبان: English
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شناسه ملی سند علمی:
ICEE21_779
تاریخ نمایه سازی: 27 مرداد 1392
Abstract:
This paper presents low power design methods for successive approximation registers (SARs) that may serve as the digital part of a successive approximation analog to digital converter (SA-ADC). The SAR is designed in 130nm technology in the sub-threshold region to meet the goal of reduced power consumption.
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Authors
Rabeeh Majidi
ECE Department, Worcester Polytechnic Institute, Worcester MA USA