Designing Efficient Hardware for Parallel CRC Computation Using OZO Polynomials

In order to provide error detection in communication networks amethod called Cyclic Redundancy Check has been used for almost 40 years. CRC is widely used in recent computer networks. Developing efficient methods for calculating CRC is a research focus nowadays. This paper proposes and evaluates a novel method for reducing the time required for calculating CRC.Our proposed approach providesboth high throughput and configurability which makes it proper for different network protocols. Since the computation of the CRC is one of the most computationalextensive operations performed by a network terminal the use of theaccelerator presented here would reduce the workload of a host processor significantly.

Keywords:

Module-2 Division , LFSR , CRC , OZO Polynomials