Designing Efficient Hardware for Parallel CRC Computation Using OZO Polynomials
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Publish Year: 1393
Type: Conference paper
Language: English
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KMTTORBAT01_031
Index date: 6 June 2015
Designing Efficient Hardware for Parallel CRC Computation Using OZO Polynomials abstract
In order to provide error detection in communication networks amethod called Cyclic Redundancy Check has been used for almost 40 years. CRC is widely used in recent computer networks. Developing efficient methods for calculating CRC is a research focus nowadays. This paper proposes and evaluates a novel method for reducing the time required for calculating CRC.Our proposed approach providesboth high throughput and configurability which makes it proper for different network protocols. Since the computation of the CRC is one of the most computationalextensive operations performed by a network terminal the use of theaccelerator presented here would reduce the workload of a host processor significantly.
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Designing Efficient Hardware for Parallel CRC Computation Using OZO Polynomials authors
Morteza Dashtban
Department of Computer Engineering and Information Technology AmirKabir University of Technology Tehran, Iran
Maryam Rezai
Department of Computer Engineering and Information Technology AmirKabir University of Technology Tehran, ran
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