A Two-Stage Monolithic Fully-Differential Op-Amp and Sample-And-Hold Circuit

A Two-Stage Fully Differential Op-Amp and 100 MSps sample and hold, implemented in 0.18-μm CMOS technology with 1.8V supply. This circuit is presented for application in analog-to-digital converter and DC-DC Converter. Topology selection, biasing and compensation are discussed. The proposed Op-Amp provides 740MHz unity-gain bandwidth (ωu), 70 degree phase margin, and a differential peak to peak output swing more than 2.2v. The designed system shows suitable response in different PVT corners.

Keywords:

Analog Integrated Circuit Design , Two-Stage Fully Differential Op-Amp , Sample and Hold Circuit , and CMOS Technology