Design of Two New High-Performance Full Adders Using Hybrid-CMOS Logic Style for Low-Power Applications

This paper, presents two new designs for a 1-bit full adder using hybrid-CMOS logic style. The new full adder cells have been formed by a few number of transistors and offers lower power consumption, propagation delay and power-delay product (PDP) than standard implementations of the 1-bit full adder cell. In proposed full adder cells, the short-circuit component of power consumption is low, because of using only one CMOS-inverter in each cell. According to the simulation results, the first proposed circuit outperforms its counterparts showing at least 15% improvement in power consumption and 18%improvement in PDP, and second proposed circuit outperforms its counterparts showing at least 13%, 24%, and 39% improvement in power consumption, propagation delay and PDP, respectively. HSpice simulations using 90nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits

Keywords:

Full Adder , High-Performance , Hybrid-CMOS , Low-Power , VLSI