Fault Tolerance in a RISC Asynchronous Processor Using Flow Graph Checking

This paper introduces a fault-tolerant asynchronous RISC microprocessor, called FTARM, which combines several error detection mechanisms to increase the fault coverage. The FTARM is implemented using the verilog. To evaluate the FTARM, different workloads were run on its implementation using the Verilog HDL. The evaluation is based on some thing about 2000 different transient and permanent single stuck-at-faults. The results show that more than 98% faults were detected. The Verilog model of FTARM is synthesized, where about 25% area overhead was observed.

Keywords:

Fault Tolerance , Watchdog Module , Flow Graph , Asynchronous Processor , TMR , Persia Synthesis Tool