Fully Digital ADCs Using Delay Element

Fully digital analog to digital converters (FD-ADC) have potential applications in very low power ICs and can be implemented in digital CMOS technology. In this paper a fully digital ADC, using a new current starved delay element, is presented. The linearity of the delay element is discussed and its impact on the overall performance of the ADC is addressed. It is shown that increasing the linearity of the delay element can increase the signal to noise plus distortion ratio (SNDR) of the FD-ADC.

Keywords:

Analog to digital converter , CMOS technology , delay element , linearity , signal to noise ratio