Fault Tolerant Reversible QCA Design using TMR and Fault Detecting by a Comparator Circuit

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware and also identifying the faulty module by a proposed Reversible QCA comparator circuit. Triple Module Redundancy (TMR) mechanism is implemented for Reversible QCA circuits to make them more Reliable. Our proposed Comparator and Detector design uses the minimum number of clocking zones and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells. QCA Designer ver.2.0.3 is used for simulation and verifying the design.

Keywords:

QCA , Reversible computing , Fault , Redundancy , TMR