A W-band Simultaneously Matched Power and Noise Low Noise Amplifier Using CMOS 0.13µm

A complete procedure for the design of W-band low noise amplifier in MMIC technology is presented. The design is based on a simultaneously power and noise matched technique. For implementing the method, scalable bilateral transistor model parameters should be first extracted. The model is also used for transmission line utilized in the amplifier circuit. In the presented method, input/output matching networks and transistor gate width have been optimized for simultaneous maximum gain and minimum noise figure. It is easily shown that due to the low gain property of amplifier at high frequency, it is unconditionally stable; so, the common source topology has superior performance compared to other topologies. In addition, better noise figure, lower size and higher gain with the same power consumption can be achieved compared with those of the cascode topology. The simulation results show a gain of better than 18dB and noise figure of 7.4dB at 94GHz while input/output return losses are better than 20dB.

Keywords:

Unilateral transistor model , Low Noise Amplifier (LNA) , W-band amplifier , Monolithic Microwave Integrated Circuit (MMIC)