Design and Simulation of an Improved 3-bit Multiplier using Voltage Ripple filter in CMOS Technology
Publish place: Fifth International Conference on Electrical and Computer Engineering with Emphasis on Indigenous Knowledge
Publish Year: 1396
Type: Conference paper
Language: English
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Document National Code:
COMCONF05_282
Index date: 11 May 2018
Design and Simulation of an Improved 3-bit Multiplier using Voltage Ripple filter in CMOS Technology abstract
In this paper, improved 3-bit multiplication arithmetic operator is proposed. In order to design a basic block for this multiplier, transmission gates are used which result in the design of fast and low-power full adders. Important features of this design are firstly, adding the voltage ripple filter structure to improve the output and secondly, the ability of the final 3-bit multiplier to operate with a 1 volt supply. All design stages of this 3-bit multiplier are performed using HSPICE in 0.18µm CMOS technology. Simulation results show that the final design has low power consumption and delay, therefore, PDP parameter reduces compared to similar designs
Design and Simulation of an Improved 3-bit Multiplier using Voltage Ripple filter in CMOS Technology Keywords:
Design and Simulation of an Improved 3-bit Multiplier using Voltage Ripple filter in CMOS Technology authors
Sina Salehi
Department of Electrical Engineering, Tehran science and research Branch, Islamic Azad University, Tehran, Iran
Maryam Nayeri
Department of Electrical Engineering, Yazd Branch, Islamic Azad University, Yazd, Iran