An Efficient FPGA Implementation of DAISY Descriptor based on Pipeline and Multicycle Architectures

DAISY descriptor is inspired of earlier descriptors such as SIFT and Gradient Location and Orientation Histogram (GLOH) but it can be computed much faster. Those earlier descriptors require a significant amount of computational power which makes them to be inappropriate for real-time applications. In this work, the Daisy descriptor is implemented on the Field Programming Gate Array (FPGA) in order to be appropriate for real-time applications. Because of high accuracy and low computational power of DAISY descriptor, a special structure for implementing this descriptor on FPGA is designed. Implementation results show that the DAISY descriptor can be computed on FPGA much faster than on CPU. Required time of dense computation of the DAISY descriptor on an image with size of 300×400 pixels is 4 milliseconds on FPGA whereas the required time on CPU is 1.2 seconds. The proposed architecture is implemented using Verilog and achieves real-time descriptor calculation on approximately 220 fps 300×400 video frames on 133 MHz clock.

An Efficient FPGA Implementation of DAISY Descriptor based on Pipeline and Multicycle Architectures Keywords:

DAISY Descriptor , FPGA Implementation , Pipeline , Multicycle , Real-time