A 10b & 0.55ps Resolution Coarse-Fine Time-to-Digital Converter in 65nm CMOS Technology Using a Linear Time Amplifier

The time measurement concept plays a critical role when it comes to processing signals from a temporal dimension, especially in different spheres of science and technology, such as in measurement tools and data converters. Due to the increasing progress in technology in the areas mentioned, increasingly, a dire need for a convertor of utmost precision is felt. The more linear the time amplifier is, the more precise it will be. This article was aimed at designing a time amplifier with a high gain and an appropriate amount of linearity, compatible with a time-to-digital convertor. This circuit contains a half-pass judger, which was meant to measure the relative position of the stop edge within the subrange of the delayed row. The additional operation helps the restriction of the remaining time-limit transferred to the fine stage. The present article was aimed at studying how improving a time amplifier can influence the performance of a 10b coarse-fine time-to-digital convertor. The results demonstrated that the resolution of the proposed circuit was 0.55ps; (the time spans were planned to be 0.1ps in this experiment). The amount of DNL was determined to be 1.5LSB. The proposed circuit was simulated using Hspice software in 65nm-CMOS technology with the 1.2v power supply.

A 10b & 0.55ps Resolution Coarse-Fine Time-to-Digital Converter in 65nm CMOS Technology Using a Linear Time Amplifier Keywords:

Time to digital converter , Time amplifier , Half-Pass-Judger