A new low power and high-speed design of 11T SRAM cell

The memory blocks and specially the SRAM cells consume high chips area and consequently these cells optimization can increase the whole system performance. Power and speed are two parameters which can improve the ability of cells. In this paper, a new eleven transistors (11T) SRAM cell is proposed that improves read speed, stability and SNM. along with lower power consumption speeds so that overall static reading margin is up to 19% better than 12 transistor memory cells. And it has a 43% improvement over a conventional six -transistor SRAM cell, and also an average reading speed is about 30% compared to a 12-transistor cell, as the number of transistors increased compared to the six-transistor cell, the power consumption decreased by about 40% and compared to the 12-cell transistor cell, the power consumption decreased dramatically by 80% for best efficiency.The circuit simulations by HSPICE in 32nm CMOS technology and 0.9v show improvement in the circuit power and speed. The proposed circuit show a significant improvement in static read and write noise margins compared to the 6T- SRAM cell. The simulation results illustrate improvements in power dissipation and reduction in read and write noise margins compared to the prior design.

Keywords:

Integrated circuit design , SRAM cell , Read stability , SNM