Tolerance Binary Comparator with Ultra-Power Saving Capability Based on Transmission Gate (TG) Technique

In this paper a new magnitude comparator based on transmission gate (TG) technique with 14 transistors is presented. The proposed circuit due to special feature of used technique has low resistivity, internal nodes and internal diffusion and parasitic capacitances. These characteristics drives the circuit with ultra-low power consumption, short paths from inputs to output for achieving high speed rate and finally high PDP dissipation savings. Various simulations using 90nm CMOS technology including VDD, frequency, temperature and load capacitances applied. Also, investigations in term of process corners and possible fabrication process using Monte Carlo performed. Attained results indicated the proposed circuit stability, tolerability, efficiency and low sensitivity to variations under different circumstances such as process voltage temperature (PVT), gate oxide thickness (tox) and diffusion doping concentration (NSD) variations. All attainment suggest the proposed circuit as an appropriate selection for being used in more sophisticated chips for future generation application

Keywords:

Digital Comparator , Full Swing , Transmission Gate , Process Voltage Temperature (PVT) Variations.