Comparing Timing Parameters in Verilog vs. HSPICE

A full adder is an important component in the design ofIntegrated Circuits. The goal of this paper is to becomefamiliar with the different layers of logic circuitssimulation. This is done here by designing a behavioralmodel of a one-bit adder in Verilog based on the timingparameters extracted from an exact simulation in Hspice.Next, a four-bit adder is designed by cascading the onebitadders in Verilog and a comparison is done betweenthe timing parameters extracted here and the parametersachieved from extracting the four-bit adder in Hspice.The propagation delays results from Verilog simulationare more than the exact results driven from the Hspice.

Keywords:

Propagation delays , Timing parameters , Fulladder , Transistor Level Simulation , Verilog , HSPICE