Hardware Implementation of Low-Power Fast Viterbi Decoder

In digital communication systems and networks, ensuring correct information reception is so important in quality of service based applications. Error Correction Coding (ECC) methods are mainly considered in order to achieve this goal. Convolutional Code is used in many wireless connections that is one of the most powerful Error Correction code and a robust way to decode this code is Viterbi algorithm. Power conception and speed are two important features of Viterbi decoders. In this paper, by removing extra cycles, the power consumption reduces by 11% and the speed increases 6 times without performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan3, Xc3s400 FPGA chip.

Keywords:

Convolutional code , Viterbi Decoder , FPGA