An Enhanced Accuracy Modeling Method for Global Interconnects in Nanoscale Technology FPGAs

Routing has a major rule in the architecture of FPGAs as one of the most important array structures [1-2]. As discussed in [1], about 90 percent die area of a FPGA is occupied by programmable routings. In this respect, the global interconnects including power, ground and clock lines, which are used to connect long paths between different blocks [1, 3], have become more important. Different models for the analysis of delay and power in interconnects are used. For short interconnects, simple models such as lumped R(L)C is sufficient, but with increasing the length, such as long and global lines, it is necessary to consider interconnect as a distributed line, particularly for Nanoscale technologies [3-5]. Also for reduction of propagation delay in aglobal line, buffer insertion is used as a useful technique [1-3, 5]. These facts are of major importance in FPGA structures of which interconnects, especially long and global, dominate transistors in terms of delay and power. In this paper a new approach for evaluating the propagation delay of the global interconnects in FPGAs is presented. One important matter is the influence of each line on the adjacent lines in a VLSI structure such as a FPGA, specially for global lines, which affects the total line delay and power. For this purpose, our new modeling technique which considers both the distributed andinfluences of global lines on each other, is proposed. Another issue is that the input of each segment in a buffer inserted global interconnect has not step waveform, which this fact affects the propagation delay of each segment and so the interconnect total propagation delay. It is shown that the propagation delay of a driven long interconnect, depends on the rise time of its input voltage signal [4]. We have assumed that the input of each segment is a ramp signal and the influence of its rise time on the propagation delay has been considered using relations discussed in [4]. Using the proposed modeling method, we have derived enhanced accuracy expressions for computation of the delay. For verification purposes, we have performed simulations for four nanoscale technology nodes 45, 65, 90 and 130 nm. The obtained results for the total propagation delay indicate 0.29% to 22.92% deviation from the HSPICE simulation results,whereas the similar deviation is 11.13% to 38.29% for the traditional Pi-model used for each segment of a long interconnect