FinFET-based Full Adder using SDTSPC Logic with High Performance

This paper presents an optimized design of SDTSPC logic (stacked diode transistor based TSPC) using FinFET transistors for ۱-bit full adder. The analysis was performed for average power consumption, leakage power, propagation delay and power delay product (PDP) for different supply voltages, loads and temperatures. Comparing the proposed FinFET-based full adder design with MOSFET-based SDTSPC full adder, we achieved a ۹۵.۷۵% improvement in leakage power consumption. The proposed scheme is also compared with several previous designs and based on different simulations, the proposed FinFET-based full adder exhibits excellent performance. The proposed high-efficiency full adder cell operates at low voltages (۰.۴ V) even with large capacitors.

Keywords:

SDTSPC (stacked diode transistor based TSPC) logic , FinFET transistor , power delay product (PDP) , TSPC logic