A 0.8-V 900-MHz CMOS Low-Noise Amplifier

Design of low-voltage low-power radio-frequency integrated circuits is of increasing importance. In this paper the effects of scaling down the feature sizes of devices on the design of low-noise amplifiers (LNA) are investigated. All available architectures for the implementation of the LNAs are compared based on the specific requirements of low-voltage low-power applications. The impact of well-known bias circuits on the amplifier’s performance is surveyed. Employing high-Q on-chip inductors allowsthis LNA to obtain a performance comparable to typical CMOS LNAs, but with an order of magnitude lower power dissipation. Available realizations for these inductors are investigated and the most economic one is chosen. The low-voltage low-power low-noise amplifier designed for use in a GSM-900 cellular receiver is simulated using HSpice with 0.25-um CMOS BSIM3v3 models. The LNA consumes 0.76 mW from a 0.8-V voltage supply. This LNA exhibits a noise figure (NF) of 2.63dB, input intercept point (IIP3) of +9dBm, forward gain (s21) of 21dB, and reverse isolation (1/s12) of +37dB

A 0.8-V 900-MHz CMOS Low-Noise Amplifier Keywords:

CMOS radio-frequency integrated circuits , low noise amplifiers , low-voltage circuit design