Reducing CMOS Gates to Equivalent Inverters Based on Modified n-th Power Law MOSFET Model

A method for modeling a CMOS gate to an effective equivalent inverter is introduced. The series-connected transistors in the NAND gate are converted to an equivalent transistor in a two step process. The model used in this conversion is the modified n-th power law which is appropriate for the state of the art logic gates. This model takes into account second order effects of submicron devices such as body effect and carrier velocity saturation. To show the validity of the technique, the calculated output waveform of the equivalent inverter is compared that of the NAND gate using HSPICE simulations (level 49).