A Systematic Method of Gate Level Approximation of Arithmetic Logic

By exploiting the feature of being error resilient of some applications and using an approximate logic, we will save power, area and time. In this paper we propose a systematic method of finding optimum approximate gate level logic whit the ability of adjusting the accuracy importance versus number of used gates in arithmetic circuits using genetic algorithm. This method will offer us a tradeoff between the number of used gates in the logic and the number of errors occurred in the truth table. We examine the proposed method performance by implementing it on full adder, full subtractor and ۲_bit_adder and compare the answers power delay area and error rate and mean relative error

Keywords:

approximate computing , approximate adder , approximate subtractor , power consumption reduction , optimization of approximate logic.