A Systematic Method of Gate Level Approximation of Arithmetic Logic

Publish Year: 1402
نوع سند: مقاله کنفرانسی
زبان: English
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شناسه ملی سند علمی:

DMECONF09_065

تاریخ نمایه سازی: 12 اردیبهشت 1403

Abstract:

By exploiting the feature of being error resilient of some applications and using an approximate logic, we will save power, area and time. In this paper we propose a systematic method of finding optimum approximate gate level logic whit the ability of adjusting the accuracy importance versus number of used gates in arithmetic circuits using genetic algorithm. This method will offer us a tradeoff between the number of used gates in the logic and the number of errors occurred in the truth table. We examine the proposed method performance by implementing it on full adder, full subtractor and ۲_bit_adder and compare the answers power delay area and error rate and mean relative error

Authors

Maryamossadat Hasheminasab

Department Computer, Faculty of Engineering, Shahid Bahonar University of Kerman,

Majid Mohammadi

Department Computer, Faculty of Engineering, Shahid Bahonar University of Kerman