A 5 GHzLow Power High Gain Optimtzed LNA for VDSM Technologies

The capability of VDSM CMOS technologies for low power, RF front-end integration is demonstrated through fully integrated low power low noise amplifiers. This pnper presents an efficient design methodology for LNAs at GHz frequencies, particularly for the range of (5.15-5.35) GHz for very deep submicron (VDSM) technologies. As design constraints for the LNA, NF (Noise Figure) is assumed to be less than 1.8 dB, and power consumption to be less than 3 mW for a 1.2 Y supply voltage. The HSPICE simulation results verifies I mW power consumption while keeping the NF=l.8 dB.

Keywords:

Low noise amplifier , LNA , noise figure , low power