At-Speed Optimal Extended Symmetric BIRA to Repair Word-Oriented Memories

With the advance of VLSI circuit’s technology andthe reduction in the size of devices, the probability of thedefects especially in embedded memories has increased. Toprevent such flaws, lots of researches have been conducted todesign Built-In Self Repair (BISR) circuits so as to prevent theyield drop get to high reliability. This paper will present an atspeedoptimal algorithm to repair single-bit errors existing inWord-Oriented memories. Although we use parallel method toget the high analysis speed, the area consumption of the circuithas decreased considerably using our optimal algorithm. Therepair rate of the proposed Built-In Redundancy Analyzer(BIRA) is also 100% because we apply the binary search treeas the base of our algorithm. The simulation results andcomparison with other methods show the efficiency of theproposed method.

Keywords:

Built-in redundancy analyser , built-in self-repair , word-oriented memory , Comprehensive Real-time ExhaustiveSearch Test and Analysis (CRESTA) , extended symmetric BIRA