Design and Characterization of Graphene Based Scannable D-Flip-Flop

Due to continuous scaling of CMOS technology current Si-based CMOS is approaching its fundamental limits. Graphene, a novel material discovered lately, is a strong contender to replace Silicon in future. Graphene has exceptional electro-mechanical properties which can be harnessed in novel devices beneficial for VLSI industry.Graphene Reconfigurable Gate (RG) proposed recently is based on steering of carriers from one end to another through back gate potential was used in realizing combinational logic gates. This paper introduces Graphene RG based Sequential elements i.e. Latch, D-Flip-Flop and Scannable D-Flip-Flop. In this paper, we focus on design and characterization of Graphene RG based sequential elements which has about 100% improvement in performance over today‟s commercial CMOS structure along with lower power consumption. More specific this paper also introduces the scan capability of the D-Flip-Flop which is a used in large scale for debug, test and program levels. This design for test (DFT) capability provides controllability and observability on the digital circuits.

Keywords:

Graphene , Graphene Reconfigurable Gate , Timing parameters , Setup time , Hold time , Power-Delay Product , Test , Scannable Flip Flop