Low Power Low Jitter CMOS Phase Frequency Detectors with Minimal Blind Zone for PLLs

In this paper, two novel open-loop phase frequency detectors have been proposed. PFD1 and PFD2 are sensitive to voltage level and edge of pulse respectively. While 58 transistors are used in conventional PFD, in this paper 20 transistors and 12 transistors are utilized for PFD1 and PFD2. Dead-Zone of the proposed open-loop PFDs are improved in compare to the open loop conventional structures where the pulse generator postpones open-loop PFD response and reduces the sensitivity. Both the designs remove reset path and are free from dead zone. Worst Case simulation results for all corners, using the BSIM3 model of a 0.18μm CMOS process when the supply voltage is subject to around 50mvolts peak-to-peak noise disturbances and layout of 2 PFDs confirm that area of the circuits has been reduced up to 46.8% for PFD1 and up to 78.4% for PFD2 when compared with conventional PFDs and it has also been observed that the power dissipation is reduced by 67.3% and 89.1 % in PFD1 and PFD2 respectively. It is proposed that both designs could be utilized for low power, high frequency and low jitter applications. In addition, these PFDs have a wide operating frequency range which can properly detect even phase difference of π/256 in whole operating frequency range.

Keywords:

Phase-Locked Loop , Phase Frequency Detector , Dead Zone , Low Power , Low Jitter PLL