Power Optimized Design Methodology for Low-Distortion Sigma-Delta-Pipeline ADCs

A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs is presented. The minimum power consumption of these converters for a given specification has achieved by dynamically exploiting the slewing and partially settling regimes of the integrators, and analytical dynamic expression for maximum possible output swing of the OTAs, which are affected by scaling factors. The proposed, precise, and yet simple approach gives in rapid and efficient design of ADCs. In order to verify the usefulness of the proposed methodology a 14-bit, 5MS/s ADC has been realized in Hspice making use of a 0.18um CMOS technology. Simulation results show that there is a good agreement between the circuit performance and the predicted by the system level design methodology.

Keywords:

Sigma-delta-pipeline ADCs , power optimization