Low Power CNTFET Based 4-2 and 5-2 Compressor

Multipliers are the most important module in many arithmetic circuits. Sometimes multipliers may use the most area or power of circuits and also may be in the critical path which leads to speed reduction. Compressors are building block of the most multipliers. In this paper, a low power architecture is proposed that can be used in compressor designs. The proposed architecture uses 3 input low power XOR Module inputs and to evaluate the power usage and delay we have used 2 different type of compressors (4-2 and 5-2). These two designs were simulated using HSPICE simulator with 32nm Stanford CNTFET and CMOS model based upon 1 Volt and 1GHz frequency operator. The results indicate that proposed compressor architectures has less PDP and power consumption in compare with the existing proposed compressors

Keywords:

4-2 Compressor , 5-2 Compressor , 3 Input XOR , Low Power , Circuit simulation