Design and Simulation of Spike-Based Learning with Generalized I&F Neuron and Astrocyte Circuit

Implementation of VLSI spike-based neural systems and networks is increasing rapidly and continuously. Designing spike -based circuits and algorithms that are well-matched with existing solutions, results and contribute these systems with adaptation, classification and organization is more important than before. The learning rule implemented in this paper is a supervised rule: an instructor signal offers the output neuron with an additional input spike-train throughout training, in corresponding to the spike-trains that signify the input pattern. The instructor signal simply shows if the neuron should answer to the input pattern with a high ratio or with a low ratio. In this paper, a VLSI implementation of generalized Integrate and Fire neuron which is coupled with synaptic circuits with spike-based learning capabilities is described. The conductance-based silicon neuron has incorporated the spike-frequency adaptation and refractory period mechanisms. The synaptic circuits unveils realistic dynamic in the post-synaptic currents and include local spike-based learning circuits. Also, the astrocyte circuit is used as a portion of spike-based learning circuit. The circuit has been designed and simulated with 0.35 µm CMOS technology in HSPICE software and it is very effective in categorizing and classifying complex patterns.

Keywords:

VLSI , Spike-based learning , Astrocyte , Integrate and Fire , Neuron