A 4.5-mW 2dB-NF 22dB-Gain Single-Stage Cascode LNA with Interstage Matching using 0.13-μm 1.2-V RF CMOS Technology

this paper presents a very high gain cascode LNA in a 0.13-um CMOS technology while consuming only 4 mA current from a 1.2-volt dc supply. The purpose was to achieve again of over 22 dB with a single-stage single-ended topology and the minimum possible die area. An interstage-matched inductorwas employed to boost the gain. A matching network including a series inductor and a parallel capacitor was used to improve theinput matching. The optimum noise impedance is controlled not only by the extra gate-source capacitor and the source inductor but by the parallel capacitor. Here, the power-constrained simultaneous noise and impedance matching is employed. The LNA showed a post-layout simulation gain of 22.2 dB with anoise figure of 2 dB while the input and output ports were fully matched. The design was a trade-off among the gain, noise figure,matching, die size and power dissipation. This paper gives a combination of advantages for the noise optimization techniqueand interstage matching gain booster technique employed in anarrow-band inductively-degenerated cascode LNA. The proposed practical technique gives the flexibility to designers toachieve the simultaneous optimum noise and impedance matching in cascode LNAs with any sort of interstage matching. Finally, the specification of this work is compared with other works as the performance improvement proof.

Keywords:

LNA , interstage , cascode , PCSNIM , noise optimization