Design of a Low-Power CMOS Comparator Circuit in Sub-Threshold Region

In this paper, a comparator circuit in the sub-threshold region is designed and simulated to minimize the powerconsumption in nano-watt scale. In this study, three comparator structures: TG, DPL and St-CMOS areintroduced and the effect of power supply and temperature variations on the power consumption, delay, powerdelayproduct and energy-delay product is analyzed and the simulation results are presented. Considering thesimulation results, it is observed that DPL technology obtains the least power consumption and power delayproduct in comparison with other structures.

Keywords:

Low-power , sub-threshold , comparator , CMOS