A Low-power, Compact, Dynamic D-type Flip-Flop for Implementation of the Digital Delay Line in a D ecision Feedback Equalizer
Publish place: 2st National Conference on Development of Civil Engineering, Architecure,Electricity and Mechanical in Iran
Publish Year: 1394
Type: Conference paper
Language: English
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Document National Code:
DCEAEM02_088
Index date: 19 February 2016
A Low-power, Compact, Dynamic D-type Flip-Flop for Implementation of the Digital Delay Line in a D ecision Feedback Equalizer abstract
A low-power, dynamic, negative-edge-triggered D-type flip-flop (D-NETFF) intended for the digital delay line in a decision feedback equalizer is proposed. The performance of the D-NETFF has been compared with that of a standard, static D-type flip-flop topology employing master-slave latches in a90nm CMOS technology based on HSPICE simulations. The positive-edge-triggered equivalent of the proposed D-type flip-flop (D-PETFF) as well as the standard static flip-flop have been designed and implemented in a 2μm CMOS technology and their performance has been characterized. Comparedwith the static flip-flop, the dynamic flip flop consumes less power, operates at higher speeds, and employs a smaller number of transistors
A Low-power, Compact, Dynamic D-type Flip-Flop for Implementation of the Digital Delay Line in a D ecision Feedback Equalizer Keywords:
A Low-power, Compact, Dynamic D-type Flip-Flop for Implementation of the Digital Delay Line in a D ecision Feedback Equalizer authors
Maryam Rajabi
Department of Electrical Engineering,Islamic Azad University, Saveh, Iran
Shahriar Jamasb
Department of Biomedical Engineering,Hamedan University of Technology, Hamedan 65169, Iran
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