A High Speed Low Power Signed Digit Adder

Signed digit (SD) number systems provide the possibility of constant-time addition, where interdigit carry propagation is eliminated. Such carry-free addition is primarily a three-step process. The special case of maximally redundant SD number systems leads to more efficient carry-free addition. This has been previously achieved based on speculation of transfer values and use of three parallel adders. We propose an alternative nonspeculative addition scheme that computes the transfer values through a fast combinational logic. The proposed carry-free addition scheme is shown to improve performance in terms of speed, power and area. The simulation and synthesis of three previous works and this work, based on 0.13 μm CMOS technology, confirms the latter claim.

Keywords:

Computer arithmetic , Carry-free addition , Signed-digit number systems , Low power design , Maximal redundancy