An Adaptive Architecture For the Bit-Serial multiplication in the Galois Fields GF(2m)

In this paper, an efficient architecture for the implementation of polynomial basis multipliers over GF(2m) is presented. The proposed architecture provides an efficient execution of the Least Significant Bit (LSB)-first, bit-serial multiplication for different operand lengths. The selection of (LSB)-first over the (MSB)-first, is its implementation suitability with reduced delay time. The main features of the proposed architecture are its hardware simplicity which results in small area implementation, flexible Galois field sizes, and improvement of maximum clock frequency with lessen critical path delay. These abilities achieved by means of employing a binary tree structure of OR gates added to the (LSB)-first multiplier.

An Adaptive Architecture For the Bit-Serial multiplication in the Galois Fields GF(2m) Keywords:

Flexible design , Galois field multiplier , Irreducible polynomial , Elliptic Curve Cryptography