23-Bit Hyper Pipeline RISC Architecture CPU

The Hyper pipelining technique which is going to be presented in this article is a modified Hyper pipeline RISC CPU which had been introduced before and is a little different to the recently introduced hyper pipeline RISC processor. Firstly we should know that the hyper pipeline is not exactly the same as famous pipelining of instruction decoding in RISC processors. The difference is that hyper pipelining can be used on top of any sequential logic. In hyper pipeline, there are not doubled or multiplied total components of any stages and just by increasing the numbers of registers, faster processor can be achieved. The RISC processor with pipelined instruction set decoding can be hyper pipelined to generate CMF individual RISC processors while CMF is a value greater than 1 and is the abbreviation of Core Multiplication factor. Hyper pipelining uses additional registers and implement register balancing for better grain timing optimizations. Hyper Pipelining Method is also named as C-slow Retiming . The major advantage is the multiplication of the core's functionality by only adding registers and not multiplying the numbers of total cores structures. This is a great advantage for ASICs but even for FPGAs with their already existing registers.

23-Bit Hyper Pipeline RISC Architecture CPU Keywords:

RISC Architecture , Hyper Pipeline , CPU , Instruction Set