High Level Comparison of Full Adders in Verilog
Publish place: اولین کنفرانس سالانه تحقیقات کاربردی در مهندسی برق، کامپیوتر
Publish Year: 1394
Type: Conference paper
Language: English
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Document National Code:
ECCONF01_005
Index date: 25 January 2017
High Level Comparison of Full Adders in Verilog abstract
Comparing different full adders is very significant for VLSI design as they are essential components in almost all digital circuits. The science has yield the benchmarking work laborious as often distinct implementation techniques and technologies have been used in the design. Additionally, the design characteristics which are selected for performance analysis are not consistent. This paper shows the results of comparing four adder structures by implementing them all with the same technology and the same level of abstraction.
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High Level Comparison of Full Adders in Verilog authors
Negin Mahnai
Shahid Bahonar University, Zarand High Education Center, Computer Engineering Faculty, Zarand, Kerman, Iran
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