Transistor Sizing Has Detectable Effects on the Circuit Speed and Performance

A one-bit full adder is a critical cell in the outline of integrated circuits. This paper speaks to a transistor design on a normally utilized 30-transistor CMOS full adder. Full adder simulation with HSPICE in CMOS 0.35μ process has exhibited that transistor sizing have detectable effects on the circuit speed and performance. Under changing size of w exhibited in this paper as demonstrated in VLSI books, speed change has been watched and it implies that the decrement of the time of propagation delay or TPD has worked out as expected. HSPICE 2003 is utilized to support our methodology.

Transistor Sizing Has Detectable Effects on the Circuit Speed and Performance Keywords:

Full Adder , HSPICE , Simulation , CMOS , Transistor Sizing