Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint
Publish place: 12th Iranian Conference on Electric Engineering
Publish Year: 1383
Type: Conference paper
Language: English
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Document National Code:
ICEE12_114
Index date: 4 October 2008
Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint abstract
A new design methodology for dual Vt domino logic design based on noise, area and power constraints is presented. We have proposed the optimum ranges for the evaluation network tree are Wmin
Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint Keywords:
Domino logic , dual threshold voltage keeper transistor , evaluation network transistor , subthreshold leakage current , skew inverter
Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint authors
A Zahabi
ECE Department University of Tehran
Y Koolivand
ECE Department University of Tehran
A Afzali-kusha
ECE Department University of Tehran
M Nourani
EE Department University of Texas
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