A new design full adder based-CNTFET with low power consumption and high-speed

In this paper, a new model for carbon nanotube field-effect transistor (CNTFET) is presented. In order to demonstrate the feasibility of the model, it is employed in a new full adder circuit and then simulation has been applied. The FETToy software and HSPICE simulator are utilized to study the model and circuit simulation. CNTFET data center for HSPICE software is improved toward the Stanford model. The simulation results demonstrate that using carbon nanotube based transistors, reduce power consumption of the circuit. Moreover, propagation delay of the circuits is obtained. Simulation results do not only verify that speed of the CNTFET based circuit is more than CMOS based circuit but also emphasize on the ability of carbon nanotube based circuits for replacing in the CMOS logical gates to improve the speed and power consumption

Keywords:

Carbon nanotube field effect transistor(CNTFET) , Full adder circuit