Hybrid domino XOR gate design with low power consumption

XOR gates are the fundamental units which are used in many VLSI applications such as adders and microprocessors, and if we can reduce their power consumption and size, it will results in optimized VLSI chips. In this paper, a domino XOR gate in 45nm technology are presented. By eliminating two input inverters and preventing the pulse flow to the output node during the precharge phase, power consumption in this circuit is reduced

Keywords:

low power , domino XOR gate , evaluation phase , precharge phase