Design of two 9 transistors Low consumption SRAM cell with improved fastness and stability

One of the most important blocks in today s digital systems are SRAM memory blocks, because these blocks are widely used as a memory cache in different types of microprocessors. Power consumption of SRAM cell consists of two components of leakage power (static) and dynamic power. Due to high volume of these cells in today’s microprocessors, their leakage power is very important. Data stability and static noise margin (SNM) in the SRAM cells with respect to reduction of supply voltage is gaining more attention. In addition to consumed power and data stability, reading and writing delay of SRAM cells has a main role to improve fastness and performance of microprocessors. In this paper, two new designs of 9 transistors cells has been proposed that are compared with four different cells with 6, 7, 8 and 9 transistors addressed in the recent literature. Simulation results show that dynamic and static power consumption of these proposed two cells are less than all other cells that are previously presented and are also faster than 6, 7 and 8 transistors cells in both reading and writing stages.

Keywords:

Data Stability , reading and writing delay , dynamic power , leakage power