Multi-bit ΔΣ modulator using single-bit single-clock quantizer

A new multi-bit ΔΣ modulator based on tracking quantizer is presented. The proposed quantizer utilizes a comparator, a single-bit digital to analogue converter (DAC) and the related control logic to predict the output of integrator into 4-bit binary code in one clock pulse. It eliminates the requirement of a flash quantizer in the multi -bit ΔΣ modulators. Therefore, the power consumption of modulator is reduced significantly and the sampling frequency can be increased without bandwidth limitation. Also, compared to the traditional tracking quantizer, a single -bit DAC is replaced with multi-level internal DAC of the quantizer that achieves a reduction of silicon area and power consumption of the proposed modulator. In order to study the performance of the proposed structure, a first-order discrete-time ΔΣ modulator is designed and simulated in 0.18 nm CMOS technology. The simulation result shows that the proposed ΔΣ modulator has a signal to noise and distortion ratio (SNDR) of 43.4 dB at 1 MHz bandwidth for Bluetooth application. The oversampling ratio (OSR) and the power consumption of the simulated modulator are 16 and 1.46 mW, respectively.

Multi-bit ΔΣ modulator using single-bit single-clock quantizer Keywords:

analogue to digital converter , ΔΣ modulator , digital to analogue converter , multi-bit quantizer , tracking quantizer