A Novel Leakage Reduction Circuit in Nanoscale Technology

Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. In this paper, we present a novel leakage reduction technique and then compare and contrast it with other well established leakage reduction techniques. In this approach achieves leakage power reduction but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered) . Based on experiments several standard CMOS gate, in this approach achieves ultra low static power consumption with state saving. In this work, we used dual Vth (voltage threshold) in novel leakage reduction circuit that this approach is the most efficient approach to reduce leakage current with the smallest delay and area increases while simultaneously preserving precise logic state in sleep mode.

Keywords:

Subthreshold Leakage Current , Low Leakage Power , Leakage Power Standby , Sleep Mode.