FPGA-based implementation of Single Precision Floating Point Arithmetic operation

Floating point numbers are utilized in the digital application like modern computers, embedded processors, digital signal processors, digital filters and signal processing application. real numbers in binary format are represented by Floating point numbers. arithmetic operations with floating-point numbers (FPN) are commonly executed using hardware. In this paper, we propose architectures for performing addition, subtraction, multiplication, division and the square root of floating-point numbers using the IEEE-754 standard. these architectures are designed using VHDL Hardware Description Language (HDL) and are implemented on Cyclone IV EP4CE30F23C7 FPGA. In this implementation, we try to use from simple units. Multiplexer, comparator, add/sub have been used in this implementation to reduce the numberof resources used.

Keywords:

Single Precision Floating Point , FPGA-based , VHDL , Hardware implementation