An Efficient FPGA Implementation of the Piccolo Block Cipher High Level Synthesis Approach

Although Radio-frequency identification (RFID) technology can streamline many applications and provide benefits, but the security and privacy of RFID systems are serious issues which need to be taken into account. Resource-efficient cryptographic incipients become basic for realizing both security and efficiency in constrained environments and embedded systems like RFID tags and sensor nodes. Among those primitives, lightweight block cipher plays a significant role as a building block for security systems. In 2011 Kyoji Shibutani et al in Sony Corporation proposed a new ultra lightweight block cipher, Piccolo, which is suitable for these types of applications. In this paper, we describe and simulate piccolo block cipher and hardware synthesize of the algorithm. Finally, we implement the Piccolo algorithm on a FPGA and express the results.

Keywords:

ultra-lightweight , block cipher , Piccolo algorithm , synthesis , implementation , Field Programmable Gate Array (FPGA)