Comparative Study of SRAM Circuit with 32nm MOSFET and CNTFET

The comparison of the conventional SRAM topology which have been implemented on CMOS 32nm and CNTFET technologies are presented here. The considered topologies have been compared for obtaining low-dissipation power characteristics. The considered architectures are implemented based on the CMOS-CNTFET echnologies. The read and write times together with the idle state has been investigated and compared for both technologies. The considered CMOS 32 nm is PTM technology while the CNTFET one is provided by Stanford. The best and lowest obtained dissipation power in the CMOS and CNTFET are reported here to be 328 μW and 46.5 nW, respectively during the read operation. On the other hand, during the write operation, the calculation results demonstrate a power drain of 15 μW for the CMOS technology and 187 nW for the CNTFET SRAM. Based on the obtained results, all the proposed topologies demonstrate significant power dissipation mitigation with respect to that of conventional SRAMS techniques while the reduction of the power consumption for the case of CNTFET is much more obvious.

Comparative Study of SRAM Circuit with 32nm MOSFET and CNTFET Keywords:

SRAM , CNTFET , CMOS